MC68HC08GZ32 Datasheet, PDF (173/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit
shift register. A 0 start bit automatically goes into the least significant bit (LSB) position of the transmit shift
register. A 1 stop bit goes into the most significant bit (MSB) position.
The ESCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the ESCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition,
logic 1. If at any time software clears the ENSCI bit in ESCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port E pins.
14.4.2.3 Break Characters
Writing a 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character.
For TXINV = 0 (output not inverted), a transmitted break character contains all logic 0s and has no start,
stop, or parity bit. Break character length depends on the M bit in SCC1 and the LINR bits in SCBR. As
long as SBK is at 1, transmitter logic continuously loads break characters into the transmit shift register.
After software clears the SBK bit, the shift register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
When LINR is cleared in SCBR, the ESCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be, resulting in a total of 10 or 11
consecutive logic 0 data bits. When LINR is set in SCBR, the ESCI recognizes a break character when a
start bit is followed by 9 or 10 logic 0 data bits and a logic 0 where the stop bit should be, resulting in a
total of 11 or 12 consecutive logic 0 data bits.
Receiving a break character has these effects on ESCI registers:
• Sets the framing error bit (FE) in SCS1
• Sets the ESCI receiver full bit (SCRF) in SCS1
• Clears the ESCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE),
or reception in progress flag (RPF) bits
14.4.2.4 Idle Characters
For TXINV = 0 (output not inverted), a transmitted idle character contains all logic 1s and has no start,
stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing
idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the character currently being transmitted.
NOTE
When a break sequence is followed immediately by an idle character, this
SCI design exhibits a condition in which the break character length is
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
173