MC68HC08GZ32 Datasheet, PDF (182/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
Address: $0013
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LOOPS ENSCI TXINV
M
WAKE
ILTY
PEN
PTY
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 14-10. ESCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the
ESCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable ESCI Bit
This read/write bit enables the ESCI and the ESCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in ESCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = ESCI enabled
0 = ESCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE
Setting the TXINV bit inverts all transmitted values including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
This read/write bit determines whether ESCI characters are eight or nine bits long (See
Table 14-5).The ninth bit can serve as a receiver wakeup signal or as a parity bit. Reset clears the M
bit.
1 = 9-bit ESCI characters
0 = 8-bit ESCI characters
Table 14-5. Character Format Selection
Control Bits
M PEN:PTY
0
0X
1
0X
0
10
0
11
1
10
1
11
Start Bits
1
1
1
1
1
1
Character Format
Data Bits Parity Stop Bits
8
None
1
9
None
1
7
Even
1
7
Odd
1
8
Even
1
8
Odd
1
Character Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
MC68HC08GZ32 Data Sheet, Rev. 3
182
Freescale Semiconductor