MC68HC08GZ32 Datasheet, PDF (224/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
BUS
CLOCK
MOSI
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
WRITE
TO SPDR
INITIATION DELAY
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
BUS
CLOCK
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
LATEST
SPSCK = BUS CLOCK ÷ 2;
2 POSSIBLE START POINTS
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SPSCK = BUS CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SPSCK = BUS CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
EARLIEST
SPSCK = BUS CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
Figure 16-8. Transmission Start Delay (Master)
For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no
more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur
until the transmission is completed. This implies that a back-to-back write to the transmit data register is
not possible. SPTE indicates when the next write can occur.
MC68HC08GZ32 Data Sheet, Rev. 3
224
Freescale Semiconductor