MC68HC08GZ32 Datasheet, PDF (192/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
PDS2–PDS0 — Prescaler Divisor Select Bits
These read/write bits select the prescaler divisor as shown in Table 14-9. Reset clears PDS2–PDS0.
NOTE
The setting of ‘000’ will bypass not only this prescaler but also the prescaler
divisor fine adjust (PDFA). It is not recommended to bypass the prescaler
while ENSCI is set, because the switching is not glitch free.
Table 14-9. ESCI Prescaler Division Ratio
PS[2:1:0]
000
001
010
011
100
101
110
111
Prescaler Divisor (PD)
Bypass this prescaler
2
3
4
5
6
7
8
PSSB4–PSSB0 — Clock Insertion Select Bits
These read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve
more timing resolution on the average prescaler frequency as shown in Table 14-10. Reset clears
PSSB4–PSSB0.
Table 14-10. ESCI Prescaler Divisor Fine Adjust
PSSB[4:3:2:1:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
Prescaler Divisor Fine Adjust (PDFA)
0/32 = 0
1/32 = 0.03125
2/32 = 0.0625
3/32 = 0.09375
4/32 = 0.125
5/32 = 0.15625
6/32 = 0.1875
7/32 = 0.21875
8/32 = 0.25
9/32 = 0.28125
10/32 = 0.3125
11/32 = 0.34375
12/32 = 0.375
13/32 = 0.40625
Continued on next page
MC68HC08GZ32 Data Sheet, Rev. 3
192
Freescale Semiconductor