MC68HC08GZ32 Datasheet, PDF (75/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6
Computer Operating Properly (COP) Module
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
CONFIG register.
6.2 Functional Description
Figure 6-1 shows the structure of the COP module.
CGMXCLK
12-BIT COP PRESCALER
RESET CIRCUIT
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COPEN (FROM SIM)
COP DISABLE
(FROM CONFIG)
RESET
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
CLEAR
COP COUNTER
COP RATE SEL
(FROM CONFIG)
Figure 6-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by the 12-bit SIM counter. If not cleared by
software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176
CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration
register. With a 8176 CGMXCLK cycle overflow option, a 4.9152-MHz crystal gives a COP timeout period
of 53.3 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by
clearing the COP counter and stages 12–5 of the SIM counter.
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
75