MC68HC08GZ32 Datasheet, PDF (286/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

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When monitor mode is entered with V_TST on IRQ, the computer operating properly (COP) is disabled as
long as V_TST is applied to either IRQ or RST.
This condition states that as long as V_TST is maintained on the IRQ pin after entering monitor mode, or if
V_TST is applied to RST after the initial reset to get into monitor mode (when V_TST was applied to IRQ),
then the COP will be disabled. In the latter situation, after V_TST is applied to the RST pin, V_TST can be
removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode.
20.3.1.2 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code. Table 20-2 summarizes the
differences between user mode and monitor mode.
Table 20-2. Mode Differences
Modes
User
Monitor
Reset
Vector High
$FFFE
$FEFE
Reset
Vector Low
$FFFF
$FEFF
Functions
Break
Break
Vector High Vector Low
$FFFC
$FFFD
$FEFC
$FEFD
SWI
Vector High
$FFFC
$FEFC
SWI
Vector Low
$FFFD
$FEFD
20.3.1.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
START
BIT BIT 0
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
NEXT
START
BIT 6 BIT 7 STOP BIT
BIT
Figure 20-11. Monitor Data Format
20.3.1.4 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of approximately two bits and then echoes back the break
signal.
MISSING STOP BIT
APPROXIMATELY 2 BITS DELAY
BEFORE ZERO ECHO
01234567
01234567
Figure 20-12. Break Transaction
20.3.1.5 Baud Rate
The communication baud rate is controlled by the crystal frequency or external clock and the state of the
PTB4 pin (when IRQ is set to V_TST) upon entry into monitor mode.
Table 20-1 also lists external frequencies required to achieve a standard baud rate of 7200 bps. The
effective baud rate is the bus frequency divided by 278. If using a crystal as the clock source, be aware
MC68HC08GZ32 Data Sheet, Rev. 3
286
Freescale Semiconductor