MC68HC08GZ32 Datasheet, PDF (203/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

OSC2
OSC1
OSCILLATOR (OSC)
CGMXCLK
OSCENINSTOP
FROM
MOR2
CGMRCLK
PHASE-LOCKED LOOP (PLL)
CGMOUT
Reset and System Initialization
TO TBM,TIM1,TIM2, ADC, MSCAN08
SIM
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF CHIP
IT23
TO REST
OF CHIP
TO MSCAN08
Figure 15-4. System Clock Signals
15.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
• Forced monitor mode entry reset (MODRST)
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 15.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). See 15.7 SIM Registers.
A reset immediately stops the operation of the instruction being executed. Reset initializes certain control
and status bits. Reset selects CGMXCLK divided by four as the bus clock.
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
203