EP2SGX30C Datasheet, PDF (96/314 Pages) Altera Corporation – Stratix II GX Device

Digital Signal Processing (DSP) Block
Table 2–23. DSP Block Signal Sources and Destinations
LAB Row at
Interface
0
1
2
3
Control Signals Generated Data Inputs Data Outputs
clock0
aclr0
ena0
mult01_saturate
addnsub1_round/
accum_round
addnsub1
signa
sourcea
sourceb
clock1
aclr1
ena1
accum_saturate
mult01_round
accum_sload
sourcea
sourceb
mode0
clock2
aclr2
ena2
mult23_saturate
addnsub3_round/
accum_round
addnsub3
sign_b
sourcea
sourceb
clock3
aclr3
ena3
accum_saturate
mult23_round
accum_sload
sourcea
sourceb
mode1
A1[17..0] OA[17..0]
B1[17..0] OB[17..0]
A2[17..0] OC[17..0]
B2[17..0] OD[17..0]
A3[17..0] OE[17..0]
B3[17..0] OF[17..0]
A4[17..0] OG[17..0]
B4[17..0] OH[17..0]
2–88
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007