EP2SGX30C Datasheet, PDF (124/314 Pages) Altera Corporation – Stratix II GX Device

I/O Structure
Figure 2–80. Control Signal Selection per IOE
Dedicated I/O
Clock [7..0]
Local
Interconnect
io_oe
Note (1)
Local
Interconnect
Local
Interconnect
io_sclr
io_aclr
Local
Interconnect
io_ce_out
Local
Interconnect
io_ce_in
Local
Interconnect
io_clk
clk_out
ce_out
sclr/spreset
clk_in
ce_in
aclr/apreset
oe
Note to Figure 2–80:
(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their
control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive
the I/O local interconnect, which then drives the control selection multiplexers.
In normal bidirectional operation, you can use the input register for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. You can use the OE register for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects. Figure 2–81
shows the IOE in bidirectional configuration.
2–116
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007