EP2SGX30C Datasheet, PDF (145/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
16 transmitter channels in I/O bank 1 or a maximum of 29 transmitter
channels in I/O banks 1 and 2. The Quartus II software can also merge
receiver and transmitter PLLs when a receiver is driving a transmitter. In
this case, one fast PLL can drive both the maximum numbers of receiver
and transmitter channels.
Table 2–38. EP2SGX30 Device Differential Channels Note (1)
Package
Transmitter/Receiver Total Channels
Transmitter
29
780-pin FineLine BGA
Receiver
31
Center Fast PLLs Package
PLL1
PLL2
16
13
17
14
Table 2–39. EP2SGX60 Device Differential Channels Note (1)
Package
780-pin FineLine BGA
1,152-pin FineLine BGA
Transmitter/Receiver Total Channels
Transmitter
29
Receiver
31
Transmitter
42
Receiver
42
Center Fast PLLs
PLL1 PLL2
16
13
17
14
21
21
21
21
Corner Fast PLLs
PLL7 PLL8
—
—
—
—
21
21
21
21
Table 2–40. EP2SGX90 Device Differential Channels Note (1)
Package
Transmitter/Receiver
Total
Channels
Transmitter
45
1,152-pin FineLine BGA
Receiver
47
Transmitter
59
1,508-pin FineLine BGA
Receiver
59
Center Fast PLLs
PLL1
PLL2
23
22
23
24
30
29
30
29
Corner Fast PLLs
PLL7
PLL8
23
22
23
24
29
29
29
29
Altera Corporation
October 2007
2–137
Stratix II GX Device Handbook, Volume 1