EP2SGX30C Datasheet, PDF (55/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
load acts as a preset when the asynchronous load data input is tied high.
When the asynchronous load/preset signal is used, the labclkena0
signal is no longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrack™ interconnects have
inherently low skew. This low skew allows the MultiTrack interconnects
to distribute clock and control signals in addition to data.
Figure 2–34 shows the LAB control signal generation circuit.
Figure 2–34. LAB-Wide Control Signals
Dedicated Row LAB Clocks
There are two unique
clock signals per LAB.
6
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk1
labclk2
syncload
labclkena0
or asyncload
or labpreset
labclkena1
labclkena2
labclr0
labclr1
synclr
Altera Corporation
October 2007
2–47
Stratix II GX Device Handbook, Volume 1