EP2SGX30C Datasheet, PDF (305/314 Pages) Altera Corporation – Stratix II GX Device

Referenced
Documents
DC and Switching Characteristics
Table 4–117 shows the JTAG timing parameters and values for
Stratix II GX devices.
Table 4–117. Stratix II GX JTAG Timing Parameters and Values
Symbol
Parameter
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
t_JSZX
t_JSXZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Min Max Unit
30
ns
12
ns
12
ns
4
ns
5
ns
9 ns
9 ns
9 ns
4
ns
5
ns
12 ns
12 ns
12 ns
This chapter references the following documents:
■ Operating Requirements for Altera Devices Data Sheet
■ PowerPlay Power Analyzer chapter in volume 3 of the Quartus II
Handbook.
■ PowerPlay Early Power Estimator (EPE) and Power Analyzer
■ Quartus II PowerPlay Analysis and Optimization Technology
■ Stratix II GX Architecture chapter in volume 1 of the Stratix II
GX Device Handbook
■ Stratix II GX Transceiver Architecture Overview chapter in volume 2 of
the Stratix II GX Device Handbook
■ volume 2, Stratix II GX Device Handbook
Altera Corporation
October 2007
4–135
Stratix II GX Device Handbook, Volume 1