EP2SGX30C Datasheet, PDF (272/314 Pages) Altera Corporation – Stratix II GX Device

Timing Model
Table 4–90. Stratix II GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 2 of 2)
I/O Standard
1.8-V HSTL CLass I
PCI
PCI-X
Differential SSTL-2
Class I
Differential SSTL-2
Class II
Differential SSTL-18
Class I
Differential SSTL-18
Class II
1.8-V differential
HSTL Class I
1.8-V differential
HSTL Class II
1.5-V differential
HSTL Class I
1.5-V differential
HSTL Class I I
HyperTransport (1)
LVPECL (1), (2)
LVDS (1)
-3 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
717
450
717
450
717
450
-4 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
717
450
717
450
717
450
-5 Speed Grade
500
400
400
500
500
500
500
500
500
500
500
640
400
640
400
640
400
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Notes to Table 4–90:
(1) The first set of numbers refers to the HIO dedicated clock pins. The second set of numbers refers to the VIO
dedicated clock pins.
(2) LVPECL is only supported on column clock pins.
4–102
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007