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EP2SGX30C Datasheet, PDF (154/314 Pages) Altera Corporation – Stratix II GX Device | |||
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Document Revision History
Table 2â42. Document Revision History (Part 4 of 6)
Date and
Document
Version
Changes Made
Updated:
â âTransmitter PLLsâ
â âTransmitter Phase Compensation FIFO
Bufferâ
â â8B/10B Encoderâ
â âByte Serializerâ
â âProgrammable Output Driverâ
â âReceiver PLL & CRUâ
â âProgrammable Pre-Emphasisâ
â âReceiver Input Bufferâ
â âControl and Status Signalsâ
â âProgrammable Run Length Violationâ
â âChannel Alignerâ
â âBasic Modeâ
â âByte Ordering Blockâ
â âReceiver Phase Compensation FIFO
Bufferâ
â âLoopback Modesâ
â âSerial Loopbackâ
â âParallel Loopbackâ
â âRegional Clock Networkâ
â âMultiVolt I/O Interfaceâ
â âHigh-Speed Differential I/O with DPA
Supportâ
Updated bulleted lists at the beginning of the
âTransceiversâ section.
Added reference to the âTransmit Bufferâ
section.
Deleted the Programmable VOD table from the
âProgrammable Output Driverâ section.
Changed âPLD Interfaceâ heading to âParallel
Data Widthâ heading in Table 2â14.
Deleted âGlobal & Regional Clock
Connections from Right Side Clock Pins &
Fast PLL Outputsâ table.
Updated notes to Tables 2â29 and 2â37.
Updated notes to Figures 2â72, 2â73 and
2â74.
Updated bulleted list in the âAdvanced I/O
Standard Supportâ section.
Summary of Changes
2â146
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007
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