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EP2SGX30C Datasheet, PDF (4/314 Pages) Altera Corporation – Stratix II GX Device | |||
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Features
â Support for multiple intellectual property megafunctions from
Altera® MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
â Support for design security using configuration bitstream
encryption
â Support for remote configuration updates
â Transceiver block features:
â High-speed serial transceiver channels with clock data recovery
(CDR) provide 600-megabits per second (Mbps) to 6.375-Gbps
full-duplex transceiver operation per channel
â Devices available with 4, 8, 12, 16, or 20 high-speed serial
transceiver channels providing up to 255 Gbps of serial
bandwidth (full duplex)
â Dynamically programmable voltage output differential (VOD)
and pre-emphasis settings for improved signal integrity
â Support for CDR-based serial protocols, including PCI Express,
Gigabit Ethernet, SDI, Alteraâs SerialLite II, XAUI, CEI-6G,
CPRI, Serial RapidIO, SONET/SDH
â Dynamic reconfiguration of transceiver channels to switch
between multiple protocols and data rates
â Individual transmitter and receiver channel power-down
capability for reduced power consumption during
non-operation
â Adaptive equalization (AEQ) capability at the receiver to
compensate for changing link characteristics
â Selectable on-chip termination resistors (100, 120, or 150 Ω) for
improved signal integrity on a variety of transmission media
â Programmable transceiver-to-FPGA interface with support for
8-, 10-, 16-, 20-, 32-, and 40-bit wide data transfer
â 1.2- and 1.5-V pseudo current mode logic (PCML) for 600 Mbps
to 6.375 Gbps (AC coupling)
â Receiver indicator for loss of signal (available only in PIPE
mode)
â Built-in self test (BIST)
â Hot socketing for hot plug-in or hot swap and power
sequencing support without the use of external devices
â Rate matcher, byte-reordering, bit-reordering, pattern detector,
and word aligner support programmable patterns
â Dedicated circuitry that is compliant with PIPE, XAUI, and
GIGE
â Built-in byte ordering so that a frame or packet always starts in
a known byte lane
â Transmitters with two PLL inputs for each transceiver block
with independent clock dividers to provide varying clock rates
on each of its transmitters
1â2
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007
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