EP2SGX30C Datasheet, PDF (111/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
Table 2–27. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
(Part 2 of 3)
Left Side Global and Regional
Clock Network Connectivity
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
PLL 1 outputs
c0
c1
c2
c3
PLL 2 outputs
c0
c1
c2
c3
PLL 7 outputs
c0
c1
c2
c3
vv
vv
vv
vv
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
vv
v
v
v
v
vv
v
v
v
v
vvv
v
v
v
vv
v
v
v
v
vv
v
v
v
v
vv
v
v
v
v
vv
v
v
v
v
vvv
v
v
v
vv
v
v
vvv
v
vv
v
v
vv
v
v
Altera Corporation
October 2007
2–103
Stratix II GX Device Handbook, Volume 1