EP2SGX30C Datasheet, PDF (144/314 Pages) Altera Corporation – Stratix II GX Device

High-Speed Differential I/O with DPA Support
Table 2–37. Supported TDO/TDI Voltage Combinations (Part 2 of 2)
Device
TDI Input
Buffer Power
Non-
VCC = 3.3 V
Stratix II GX
VCC = 2.5 V
VCC = 1.8 V
VCC = 1.5 V
Stratix II GX TDO V_{C C I O} Voltage Level in I/O Bank 4
V_{C C I O} = 3.3 V
v (1)
v (1), (4)
v (1), (4)
v (1), (4)
V_{C C I O} = 2.5 V
v (2)
v (2)
v (2), (5)
v (2), (5)
V_{C C I O} = 1.8 V V_{C C I O} = 1.5 V V_{C C I O} = 1.2 V
v (3)
Level shifter Level shifter
required
required
v (3)
Level shifter Level shifter
required
required
v
Level shifter Level shifter
required
required
v (6)
v
v
Notes to Table 2–37:
(1) The TDO output buffer meets V_OH (MIN) = 2.4 V.
(2) The TDO output buffer meets V_OH (MIN) = 2.0 V.
(3) An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
(4) Input buffer must be 3.3-V tolerant.
(5) Input buffer must be 2.5-V tolerant.
(6) Input buffer must be 1.8-V tolerant.
High-Speed
Differential I/O
with DPA
Support
Stratix II GX devices contain dedicated circuitry for supporting
differential standards at speeds up to 1 Gbps. The LVDS differential I/O
standards are supported in the Stratix II GX device. In addition, the
LVPECL I/O standard is supported on input and output clock pins on the
top and bottom I/O banks.
The high-speed differential I/O circuitry supports the following
high-speed I/O interconnect standards and applications:
■ SPI-4 Phase 2 (POS-PHY Level 4)
■ SFI-4
■ Parallel RapidIO standard
There are two dedicated high-speed PLLs in the EP2SGX30 device and
four dedicated high-speed PLLs in the EP2SGX60, EP2SGX90, and
EP2SGX130 devices to multiply reference clocks and drive high-speed
differential SERDES channels.
Tables 2–38 through 2–41 show the number of channels that each Fast
PLL can clock in each of the Stratix II GX devices. In Tables 2–38 through
2–41, the first row for each transmitter or receiver provides the number of
channels driven directly by the PLL. The second row below it shows the
maximum channels a Fast PLL can drive if cross bank channels are used
from the adjacent center Fast PLL. For example, in the 780-pin
FineLine BGA EP2SGX30 device, PLL 1 can drive a maximum of
2–136
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007