EP2SGX30C Datasheet, PDF (303/314 Pages) Altera Corporation – Stratix II GX Device

DC and Switching Characteristics
Table 4–113. DQS Jitter Specifications for DLL-Delayed Clock (t_DQS__JITTER)
Note (1)
Number of DQS Delay Buffer Stages
(2)
Commercial (ps)
1
80
2
110
3
130
4
160
Industrial (ps)
110
130
180
210
Notes to Table 4–113:
(1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on
two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
(2) Delay stages used for requested DQS phase shift are reported in a project’s
Compilation Report in the Quartus II software.
Table 4–114. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t_DQS__PSERR)
Number of DQS Delay Buffer Stages (1) –3 Speed Grade (ps) –4 Speed Grade (ps) –5 Speed Grade (ps)
1
25
30
35
2
50
60
70
3
75
90
105
4
100
120
140
Note to Table 4–114:
(1) Delay stages used for request DQS phase shift are reported in a project’s Compilation Report in the Quartus II
software. For example, phase-shift error on two delay stages under -3 conditions is 50 ps peak-to-peak or 25 ps.
Table 4–115. DQS Bus Clock Skew Adder Specifications
(t_DQS_CLOCK_SKEW_ADDER)
Mode
4 DQ per DQS
9 DQ per DQS
18 DQ per DQS
36 DQ per DQS
DQS Clock Skew Adder (ps) (1)
40
70
75
95
Note to Table 4–115:
(1) This skew specification is the absolute maximum and minimum skew. For
example, skew on a 40 DQ group is 40 ps or 20 ps.
Altera Corporation
October 2007
4–133
Stratix II GX Device Handbook, Volume 1