EP2SGX30C Datasheet, PDF (52/314 Pages) Altera Corporation – Stratix II GX Device

Logic Array Blocks
Logic Array
Blocks
Applications and Protocols Supported with Stratix II GX Devices
Each Stratix II GX transceiver block is designed to operate at any serial bit
rate from 600 Mbps to 6.375 Gbps per channel. The wide data rate range
allows Stratix II GX transceivers to support a wide variety of standards
and protocols, such as PCI Express, GIGE, SONET/SDH, SDI, OIF-CEI,
and XAUI. Stratix II GX devices are ideal for many high-speed
communication applications, such as high-speed backplanes,
chip-to-chip bridges, and high-speed serial communications links.
Example Applications Support for Stratix II GX
Stratix II GX devices can be used for many applications, including:
■ Traffic management with various levels of quality of service (QoS)
and integrated serial backplane interconnect
■ Multi-port single-protocol switching (for example, PCI Express,
GIGE, XAUI switch, or SONET/SDH)
Each logic array block (LAB) consists of eight adaptive logic modules
(ALMs), carry chains, shared arithmetic chains, LAB control signals, local
interconnects, and register chain connection lines. The local interconnect
transfers signals between ALMs in the same LAB. Register chain
connections transfer the output of an ALM register to the adjacent ALM
register in a LAB. The Quartus II Compiler places associated logic in a
LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,
and register chain connections for performance and area efficiency.
Table 2–17 shows Stratix II GX device resources. Figure 2–32 shows the
Stratix II GX LAB structure.
Table 2–17. Stratix II GX Device Resources
Device
EP2SGX30
EP2SGX60
EP2SGX90
EP2SGX130
M512 RAM
M4K RAM
Columns/Blocks Columns/Blocks
6/202
4/144
7/329
5/255
8/488
6/408
9/699
7/609
M-RAM
Blocks
1
2
4
6
DSP Block
Columns/Blocks
2/16
3/36
3/48
3/63
LAB
Columns
49
62
71
81
LAB Rows
36
51
68
87
2–44
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007