EP2SGX30C Datasheet, PDF (22/314 Pages) Altera Corporation – Stratix II GX Device

Transceivers
Pre-emphasis percentage is defined as (V_MAX/V_MIN – 1) × 100, where
V_MAX is the differential emphasized voltage (peak-to-peak) and V_MIN is
the differential steady-state voltage (peak-to-peak).
Programmable Termination
The programmable termination can be statically set in the Quartus II
software. The values are 100 Ω , 120 Ω , 150 Ω , and external termination.
Figure 2–11 shows the setup for programmable termination.
Figure 2–11. Programmable Transmitter Terminations
Programmable
Output
Driver
V_CM
50, 60, or 75 9
PCI Express Receiver Detect
The Stratix II GX transmitter buffer has a built-in receiver detection circuit
for use in PIPE mode. This circuit provides the ability to detect if there is
a receiver downstream by sending out a pulse on the channel and
monitoring the reflection. This mode requires the transmitter buffer to be
tri-stated (in electrical idle mode).
PCI Express Electric Idles (or Individual Transmitter Tri-State)
The Stratix II GX transmitter buffer supports PCI Express electrical idles.
This feature is only active in PIPE mode. The tx_forceelecidle port
puts the transmitter buffer in electrical idle mode. This port is available in
all PCI Express power-down modes and has specific usage in each mode.
Receiver Path
This section describes the data path through the Stratix II GX receiver. The
Stratix II GX receiver consists of the following blocks:
■ Receiver differential input buffer
■ Receiver PLL lock detector, signal detector, and run length checker
■ Clock/data recovery (CRU) unit
■ Deserializer
■ Pattern detector
■ Word aligner
2–14
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007