EP2SGX30C Datasheet, PDF (87/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
Figure 2–56. M-RAM Row Unit Interface to Interconnect
C4 Interconnect
R4 and R24 Interconnects
M-RAM Block
LAB
16
Direct Link
Interconnects
Up to 16
dataout_a[ ]
Up to 28
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
byteena_a[ ]
clocken_a
clock_a
aclr_a
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
Altera Corporation
October 2007
2–79
Stratix II GX Device Handbook, Volume 1