EP2SGX30C Datasheet, PDF (231/314 Pages) Altera Corporation – Stratix II GX Device

DC and Switching Characteristics
3. Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS model or capacitance value to
represent the load.
4. Record the time to V_MEAS.
5. Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 4–53 using the above equation. Figure 4–8 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
Figure 4–8. Output Delay Timing Reporting Setup Modeled by Quartus II
V_TT
V_CCIO
R_T
Output ^Output
R_S
Buffer
V_MEAS
C_L
Output_p
R_D
Output_n
GND
GND
Notes to Figure 4–8:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2) V_CCPD is 3.085 V unless otherwise specified.
(3) V_CCINT is 1.12 V unless otherwise specified.
Table 4–53. Output Timing Measurement Methodology for Output Pins (Part 1 of 2) Notes (1), (2), (3)
I/O Standard
LVTTL (4)
LVCMOS (4)
2.5 V (4)
1.8 V (4)
1.5 V (4)
R_S (Ω)
Loading and Termination
Measurement
Point
R_D (Ω)
R_T (Ω)
V_CCIO (V)
3.135
3.135
2.375
1.710
1.425
V_TT (V)
C_L (pF)
0
0
0
0
0
V_MEAS (V)
1.5675
1.5675
1.1875
0.855
0.7125
Altera Corporation
October 2007
4–61
Stratix II GX Device Handbook, Volume 1