EP2SGX30C Datasheet, PDF (304/314 Pages) Altera Corporation – Stratix II GX Device

JTAG Timing Specifications
Table 4–116. DQS Phase Offset Delay Per Stage (ps) Notes (1), (2), (3)
Speed Grade
-3
-4
-5
Positive Offset
Min
Max
10
15
10
15
10
16
Negative Offset
Min
Max
8
11
8
11
8
12
Notes to Table 4–116:
(1) The delay settings are linear.
(2) The valid settings for phase offset are -32 to +31.
(3) The typical value equals the average of the minimum and maximum values.
JTAG Timing
Specifications
Figure 4–14 shows the timing requirements for the JTAG signals
Figure 4–14. Stratix II GX JTAG Waveforms.
TMS
TDI
TCK
TDO
Signal
to be
Captured
Signal
to be
Driven
t _JCP
t _JCH
t _JCL
t _JPSU
t_JPZX
t_JSSU
t_JPCO
t_JSH
t_JSZX
t_JSCO
t _JPH
t _JPXZ
t_JSXZ
4–134
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007