EP2SGX30C Datasheet, PDF (277/314 Pages) Altera Corporation – Stratix II GX Device

DC and Switching Characteristics
Table 4–92. Stratix II GX Maximum Output Clock Rate for Row Pins (Part 2 of 2)
I/O Standard
Differential
SSTL-2 Class I
Differential
SSTL-2 Class II
Differential
SSTL-18 Class I
LVDS
HyperTransport
Drive Strength
8 mA
12 mA
16 mA (1)
4 mA
6 mA
8 mA
10 mA (1)
-
-
-3 Speed Grade -4 Speed Grade -5 Speed Grade
400
300
300
400
400
350
350
350
300
200
150
150
350
250
200
450
300
300
500
400
400
717
717
640
717
717
640
Note to Table 4–92:
(1) This is the default setting in Quartus II software.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4–93 shows the maximum output clock toggle rate for Stratix II GX
device dedicated clock pins.
Table 4–93. Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 1 of 4)
I/O Standard
LVTTL
LVCMOS
Drive Strength
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA (1)
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA (1)
-3 Speed
Grade
270
435
580
720
875
1030
290
565
790
1020
1066
1100
-4 Speed
Grade
225
355
475
594
700
794
250
480
710
925
985
1040
-5 Speed
Grade
210
325
420
520
610
670
230
440
670
875
935
1000
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Altera Corporation
October 2007
4–107
Stratix II GX Device Handbook, Volume 1