EP2SGX30C Datasheet, PDF (147/314 Pages) Altera Corporation – Stratix II GX Device

Figure 2–88. Stratix II GX Transmitter Channel
Data from R4, R24, C4, or
direct link interconnect
10
10
Stratix II GX Architecture
+
Up to 1 Gbps
–
refclk
Local
Interconnect
diffioclk
Fast
PLL
load_en
Dedicated
Transmitter
Interface
Regional or
global clock
Each Stratix II GX receiver channel features a DPA block for phase
detection and selection, a SERDES, a synchronizer, and a data realigner
circuit. You can bypass the dynamic phase aligner without affecting the
basic source-synchronous operation of the channel. In addition, you can
dynamically switch between using the DPA block or bypassing the block
via a control signal from the logic array.
Altera Corporation
October 2007
2–139
Stratix II GX Device Handbook, Volume 1