EP2SGX30C Datasheet, PDF (149/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
For high-speed source synchronous interfaces such as POS-PHY 4 and the
Parallel RapidIO standard, the source synchronous clock rate is not a
byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols because the source synchronous clock does
not provide a byte or word boundary since the clock is one half the data
rate, not one eighth. The Stratix II GX device’s high-speed differential I/O
circuitry provides dedicated data realignment circuitry for
user-controlled byte boundary shifting. This simplifies designs while
saving ALM resources. You can use an ALM-based state machine to
signal the shift of receiver byte boundaries until a specified pattern is
detected to indicate byte alignment.
Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left side of the device has one receiver channel and one
transmitter channel per LAB row. Figure 2–90 shows the fast PLL and
channel layout in the EP2SGX30C/D and EP2SGX60C/D devices.
Figure 2–91 shows the fast PLL and channel layout in EP2SGX60E,
EP2SGX90E/F, and EP2SGX130G devices.
Figure 2–90. Fast PLL and Channel Layout in the EP2SGX30C/D and EP2SGX60C/D Devices
4
LVDS
Clock
4
2
Fast
PLL 1
DPA
Clock
Quadrant
Quadrant
Note (1)
Fast
PLL 2
2
LVDS
4
Clock
DPA
Clock
Quadrant
Note to Figure 2–90:
(1) See Table 2–38 for the number of channels each device supports.
Quadrant
Altera Corporation
October 2007
2–141
Stratix II GX Device Handbook, Volume 1