EP2SGX30C Datasheet, PDF (19/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
Serializer (Parallel-to-Serial Converter)
The serializer converts the parallel 8, 10, 16, or 20-bit data into a serial data
bit stream, transmitting the least significant bit (LSB) first. The serialized
data stream is then fed to the high-speed differential transmit buffer.
Figure 2–7 is a diagram of the serializer.
Figure 2–7. Serializer Note (1)
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
10
D4
D4
D3
D3
D2
D2
Low-speed
parallel clock
D1
D1
Serial data
D0
D0
out (to output
buffer)
High-speed
serial clock
Note to Figure 2–7:
(1) This is a 10-bit serializer. The serializer can also convert 8, 16, and 20 bits of data.
Transmit Buffer
The Stratix II GX transceiver buffers support the 1.2- and 1.5-V PCML
I/O standard at rates up to 6.375 Gbps. The common mode voltage (V_CM)
of the output driver is programmable. The following V_CM values are
available when the buffer is in 1.2- and 1.5-V PCML.
■ V_CM = 0.6 V
■ V_CM = 0.7 V
Altera Corporation
October 2007
2–11
Stratix II GX Device Handbook, Volume 1