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EP2SGX30C Datasheet, PDF (103/314 Pages) Altera Corporation – Stratix II GX Device | |||
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Stratix II GX Architecture
Figures 2â67 through 2â69 show the clock control block for the global
clock, regional clock, and PLL external clock output, respectively.
Figure 2â67. Global Clock Control Blocks
CLKp
Pins
PLL Counter 2
Outputs
CLKSELECT[1..0]
(1)
2
2
CLKn
Pin
Internal
Logic
This multiplexer supports
User-Controllable
Dynamic Switching
Static Clock Select (2)
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 2â67:
(1) These clock select signals can be dynamically controlled through internal logic when the device is operating in user
mode.
(2) These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object
File [.pof]) and cannot be dynamically controlled during user mode operation.
Figure 2â68. Regional Clock Control Blocks
PLL Counter
Outputs
CLKp CLKn
Pin Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 2â68:
(1) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
controlled during user mode operation.
(2) Only the CLKn pins on the top and bottom of the device feed to regional clock select.
Altera Corporation
October 2007
2â95
Stratix II GX Device Handbook, Volume 1
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