EP2SGX30C Datasheet, PDF (287/314 Pages) Altera Corporation – Stratix II GX Device

DC and Switching Characteristics
Table 4–97. Maximum Output Clock Toggle Rate Derating Factors (Part 5 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
Drive
Strength
Column I/O Pins
Row I/O Pins
Dedicated Clock
Outputs
-3
-4
-5
-3
-4 -5 -3 -4 -5
1.5-V differential
16 mA
95
101 101
-
-
-
96 101 101
HSTL Class II (3)
18 mA
95
100 100
-
-
-
101 100 100
20 mA
94
101 101
-
-
-
104 101 101
3.3-V PCI
134 177 177
-
-
-
143 177 177
3.3-V PCI-X
134 177 177
-
-
-
143 177 177
LVDS
-
-
- 155 (1) 155 155 134 134 134
(1) (1)
LVPECL (4)
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
3.3-V LVCMOS
1.5-V LVCMOS
-
OCT 50 Ω 133
OCT 50 Ω 207
OCT 50 Ω 151
OCT 50 Ω 300
OCT 50 Ω 157
-
-
-
-
-
134 134 134
152 152 133 152 152 147 152 152
274 274 207 274 274 235 274 274
165 165 151 165 165 153 165 165
316 316 300 316 316 263 316 316
171 171 157 171 171 174 171 171
SSTL-2 Class I
OCT 50 Ω 121
134 134 121 134 134 77 134 134
SSTL-2 Class II OCT 25 Ω 56
101 101
56 101 101 58 101 101
SSTL-18 Class I OCT 50 Ω 100 123 123 100 123 123 106 123 123
SSTL-18 Class II OCT 25 Ω 61
110 110
-
-
-
59 110 110
1.2-V HSTL (2)
OCT 50 Ω 95
-
-
-
-
-
95
-
-
Notes to Table 4–97:
(1) For LVDS output on row I/O pins the toggle rate derating factors apply to loads larger than 5 pF. In the derating
calculation, subtract 5 pF from the intended load value in pF for the correct result. For a load less than or equal to
5 pF, refer to Tables 4–91 through 4–95 for output toggle rates.
(2) 1.2-V HSTL is only supported on column I/O pins on -3 devices.
(3) Differential HSTL and SSTL is only supported on column clock and DQS outputs.
(4) LVPECL is only supported on column clock outputs.
Altera Corporation
October 2007
4–117
Stratix II GX Device Handbook, Volume 1