EP2SGX30C Datasheet, PDF (301/314 Pages) Altera Corporation – Stratix II GX Device

DC and Switching Characteristics
Table 4–110. Enhanced PLL Specifications (Part 2 of 2)
Name
f_SS
% spread
t_{P L L _ P S E R R}
t_ARESET
t_{ARESET_RECONFIG}
t_RECONFIGWAIT
Description
Min
Spread-spectrum modulation frequency
100
Percent down spread for a given clock
0.4
frequency
Accuracy of PLL phase shift
Minimum pulse width on areset signal. 10
Minimum pulse width on the areset
500
signal when using PLL reconfiguration.
Reset the PLL after scandone goes high.
The time required for the wait after the
reconfiguration is done and the areset is
applied.
Typ
Max Unit
500
kHz
0.5
0.6
%
±30
ps
ns
ns
2
us
Notes to Table 4–110:
(1) This is limited by the I/O f_MAX. See Tables 4–91 through 4–95 for the maximum.
(2) If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
Table 4–111. Fast PLL Specifications (Part 1 of 2)
Name
f_IN
f_INPFD
f_INDUTY
t_INJITTER
f_VCO
f_OUT
Description
Min
Typ
Input clock frequency (for -3 and -4 speed
16
grade devices)
Input clock frequency (for -5 speed grade
16
devices)
Input frequency to the PFD
16
Input clock duty cycle
40
Input clock jitter tolerance in terms of period
0.5
jitter. Bandwidth ≤2 MHz
Input clock jitter tolerance in terms of period
1.0
jitter. Bandwidth > 0.2 MHz
Upper VCO frequency range for –3 and –4 300
speed grades
Upper VCO frequency range for –5 speed 300
grades
Lower VCO frequency range for –3 and –4 150
speed grades
Lower VCO frequency range for –5 speed 150
grades
PLL output frequency to GCLK or RCLK
4.6875
PLL output frequency to LVDS or DPA clock 150
Max Unit
717 MHz
640 MHz
500 MHz
60
%
ns (p-p)
ns (p-p)
1,040 MHz
840 MHz
520 MHz
420 MHz
550
1,040
MHz
MHz
Altera Corporation
October 2007
4–131
Stratix II GX Device Handbook, Volume 1