EP2SGX30C Datasheet, PDF (288/314 Pages) Altera Corporation – Stratix II GX Device

Duty Cycle Distortion
Duty Cycle
Distortion
Duty cycle distortion (DCD) describes how much the falling edge of a
clock is off from its ideal position. The ideal position is when both the
clock high time (CLKH) and the clock low time (CLKL) equal half of the
clock period (T), as shown in Figure 4–11. DCD is the deviation of the
non-ideal falling edge from the ideal falling edge, such as D1 for the
falling edge A and D2 for the falling edge B (see Figure 4–11). The
maximum DCD for a clock is the larger value of D1 and D2.
Figure 4–11. Duty Cycle Distortion
Ideal Falling Edge
CLKH = T/2
CLKL = T/2
D1 D2
Falling Edge A
Falling Edge B
Clock Period (T)
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure 4–11, is clock-period independent. DCD can also be expressed as a
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as:
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions (Figure 4–12). Therefore, any
DCD present on the input clock signal or caused by the clock input buffer
or different input I/O standard does not transfer to the output signal.
4–118
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007