EP2SGX30C Datasheet, PDF (112/314 Pages) Altera Corporation – Stratix II GX Device

PLLs and Clock Networks
Table 2–27. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
(Part 3 of 3)
Left Side Global and Regional
Clock Network Connectivity
PLL 8 outputs
c0
c1
c2
c3
vv
vv
vv
vv
v
v
v
v
v
v
v
v
2–104
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007