EP2SGX30C Datasheet, PDF (101/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
IOE clocks have row and column block regions that are clocked by 8 I/O
clock signals chosen from the 24 quadrant clock resources. Figures 2–65
and 2–66 show the quadrant relationship to the I/O clock regions.
Figure 2–65. EP2SGX30 Device I/O Clock Groups
IO_CLKA[7..0]
IO_CLKB[7..0]
8
8
I/O Clock Regions
8
IO_CLKH[7..0]
24 Clocks in
the Quadrant
24 Clocks in
the Quadrant
IO_CLKC[7..0]
8
8
IO_CLKG[7..0]
24 Clocks in
the Quadrant
24 Clocks in
the Quadrant
8
8
IO_CLKF[7..0]
IO_CLKE[7..0]
IO_CLKD[7..0]
8
Altera Corporation
October 2007
2–93
Stratix II GX Device Handbook, Volume 1