EP2SGX30C Datasheet, PDF (312/314 Pages) Altera Corporation – Stratix II GX Device

Referenced Documents
Figure 5–1. Stratix II GX Device Packaging Ordering Information
Family Signature
EP2SGX: Stratix II GX
Device Type
30
60
90
130
EP2SGX 130 G F
40
C
3
ES
Optional Suffix
Indicates specific device options or
shipment method.
ES: Engineering sample
N: Lead free
NES: Lead-free engineering sample
Speed Grade
3, 4, or 5, with 3 being the fastest
Number of
Transceiver
Channels
C: 4
D: 8
E: 12
F: 16
G: 20
Package Type
F: FineLine BGA
Operating Temperature
C: Commercial temperature (t_J = 0˚ C to 85˚ C)
I: Industrial temperature (t_J = −40˚ C to 100˚ C)
Pin Count
780
1,152 ₍₁₎
1,508
Note to Figure 5–1:
(1) Product code notations for ES silicon for all EP2SGX130 family members (standard and lead free) and EP2SGX90
(lead free) use the following codings to denote pin count: 35 for 1152-pin devices and 40 for 1508-pin devices
Referenced
Documents
This chapter references the following documents:
■ Package Information for Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II GX Device Handbook
■ Pin-Out Files for Altera Devices
■ Quartus II Development Software Handbook
Document
Table 5–1 shows the revision history for this chapter.
Revision History
Table 5–1. Document Revision History (Part 1 of 2)
Date and
Document
Version
August 2007
v1.3
Changes Made
Added the “Referenced Documents” section.
Minor text edits.
Summary of Changes
5–2
Stratix II GX Device Handbook, Volume 1
Altera Corporation
August 2007