EP2SGX30C Datasheet, PDF (40/314 Pages) Altera Corporation – Stratix II GX Device

Transceivers
Figure 2–25 shows the data path in parallel loopback mode.
Figure 2–25. Stratix II GX Block in Parallel Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST PRBS
Generator
FPGA
Logic
Array
TX Phase
Compensation
FIFO
BIST
Incremental
Verify
Byte
Serializer
RX Phase
Compen-
sation
FIFO
Byte
Ordering
8B/10B
Encoder
20
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
Analog Receiver and
Transmitter Logic
Serializer
Parallel
Loopback
BIST
PRBS
Verify
Deskew
FIFO
Word
Aligner
De-
serializer
Clock
Recovery
Unit
Receiver Digital Logic
Reverse Serial Loopback
The reverse serial loopback mode uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, passes through the CRU
unit, and the retimed serial data is looped back and transmitted though
the high-speed differential transmitter output buffer.
2–32
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007