EP2SGX30C Datasheet, PDF (47/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
Table 2–11 summarizes the possible clocking connections for the
transceivers.
Table 2–11. Available Clocking Connections for Transceivers
Source
Transmitter
PLL
Destination
Receiver PLL Global Clock
REFCLK[1..0]
v
v
v
Transmitter PLL
v
Receiver PLL
v
Global clock
(driven from an
v
v
input pin)
Inter-transceiver
lines
v
v
Regional
Clock
v
v
v
Inter-Transceiver
Lines
v
Clock Resource for PLD-Transceiver Interface
For the regional or global clock network to route into the transceiver, a
local route input output (LRIO) channel is required. Each LRIO clock
region has up to eight clock paths and each transceiver block has a
maximum of eight clock paths for connecting with LRIO clocks. These
resources are limited and determine the number of clocks that can be used
between the PLD and transceiver blocks. Table 2–12 shows the number of
LRIO resources available for Stratix II GX devices with different numbers
of transceiver blocks.
Tables 2–12 through 2–15 show the connection of the LRIO clock resource
to the transceiver block.
Table 2–12. Available Clocking Connections for Transceivers in 2SGX30D
Region
Region0
8 LRIO clock
Region1
8 LRIO clock
Clock Resource
Transceiver
Global
Clock
v
Regional Bank 13
Clock 8 Clock I/O
RCLK 20-27
v
Bank 14
8 Clock I/O
v
RCLK 12-19
v
Altera Corporation
October 2007
2–39
Stratix II GX Device Handbook, Volume 1