EP2SGX30C Datasheet, PDF (69/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
allowing fast horizontal connections to TriMatrix memory and DSP
blocks. A shared arithmetic chain can continue as far as a full column.
Similar to the carry chains, the shared arithmetic chains are also top- or
bottom-half bypassable. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in a LAB while leaving the
other half available for narrower fan-in functionality. Every other LAB
column is top-half bypassable, while the other LAB columns are
bottom-half bypassable. Refer to “MultiTrack Interconnect” on page 2–63
for more information on shared arithmetic chain interconnect.
Register Chain
In addition to the general routing outputs, the ALMs in a LAB have
register chain outputs. The register chain routing allows registers in the
same LAB to be cascaded together. The register chain interconnect allows
a LAB to use LUTs for a single combinational function and the registers
to be used for an unrelated shift register implementation. These resources
speed up connections between ALMs while saving local interconnect
resources (see Figure 2–45). The Quartus II Compiler automatically takes
advantage of these resources to improve utilization and performance. See
“MultiTrack Interconnect” on page 2–63 for more information about
register chain interconnect.
Altera Corporation
October 2007
2–61
Stratix II GX Device Handbook, Volume 1