EP2SGX30C Datasheet, PDF (151/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
■ Stratix II Performance and Logic Efficiency Analysis White Paper
■ TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX Devices
chapter in volume 2 of the Stratix II GX Device Handbook
Document
Table 2–42 shows the revision history for this chapter.
Revision History
Table 2–42. Document Revision History (Part 1 of 6)
Date and
Document
Version
Changes Made
October 2007,
v2.2
Updated:
● “Programmable Pull-Up Resistor”
● “Reverse Serial Pre-CDR Loopback”
● “Receiver Input Buffer”
● “Pattern Detection”
● “Control and Status Signals”
● “Individual Power Down and Reset for the
Transmitter and Receiver”
Updated:
● Figure 2–14
● Figure 2–26
● Figure 2–27
● Figure 2–86 (notes only)
● Figure 2–87
Updated:
● Table 2–4
● Table 2–7
Removed note from Table 2–31.
Removed Tables 2-2, 2-7, and 2-8.
Minor text edits.
August 2007, v2.1 Added “Reverse Serial Pre-CDR Loopback”
section.
Updated Table 2–2.
Added “Referenced Documents” section.
Summary of Changes
Altera Corporation
October 2007
2–143
Stratix II GX Device Handbook, Volume 1