EP2SGX30C Datasheet, PDF (125/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
Figure 2–81. Stratix II GX IOE in Bidirectional I/O Configuration
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
Note (1)
oe
clkout
ce_out
aclr/apreset
Chip-Wide Reset
sclr/spreset
clkin
ce_in
OE Register
D
Q
ENA
CLRN/PRN
OE Register
t_CO Delay
V_{CCIO PCI Clamp (2)}
V_CCIO
Programmable
Pull-Up
Resistor
Output Register
D
Q
Output
Pin Delay
ENA
Drive Strength Control
CLRN/PRN Open-Drain Output
Input Pin to
Logic Array Delay
Input Register
D
Q
Input Pin to
Input Register Delay
On-Chip
Termination
Bus-Hold
Circuit
ENA
CLRN/PRN
Notes to Figure 2–81:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The optional PCI clamp is only available on column I/O pins.
The Stratix II GX device IOE includes programmable delays that can be
activated to ensure input IOE register-to-logic array register transfers,
input pin-to-logic array register transfers, or output IOE register-to-pin
transfers.
Altera Corporation
October 2007
2–117
Stratix II GX Device Handbook, Volume 1