EP2SGX30C Datasheet, PDF (268/314 Pages) Altera Corporation – Stratix II GX Device

Timing Model
Table 4–87. Stratix II GX I/O Output Delay for Row Pins (Part 4 of 4)
I/O Standard
Drive
Strength
Fast Corner
Parameter Industrial/
Commercial
-3 Speed
Grade (3)
-3 Speed
Grade (4)
-4 Speed
Grade
-5 Speed
Grade
Unit
Differential
4 mA
t_OP
SSTL-18 Class I
t_DIP
6 mA
t_OP
t_DIP
8 mA
t_OP
t_DIP
10 mA
t_OP
t_DIP
LVDS (2)
-
t_OP
t_DIP
HyperTransport
-
t_OP
t_DIP
1038
995
1042
999
1018
975
1021
978
1067
1024
1053
1010
1709
1654
1648
1593
1633
1578
1615
1560
1723
1668
1723
1668
1793
1736
1729
1672
1713
1656
1694
1637
1808
1751
1808
1751
1906
1846
1838
1778
1821
1761
1801
1741
1922
1862
1922
1862
2046 ps
1973 ps
1975 ps
1902 ps
1958 ps
1885 ps
1937 ps
1864 ps
2089 ps
2016 ps
2089 ps
2016 ps
Notes to Table 4–87:
(1) This is the default setting in the Quartus II software.
(2) The parameters are only available on the left side of the device.
(3) This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
(4) This column refers to –3 speed grades for EP2SGX130 devices.
Maximum Input and Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Tables 4–88 through 4–90 specify the maximum input clock toggle rates.
Tables 4–91 through 4–96 specify the maximum output clock toggle rates
at 0 pF load. Table 4–97 specifies the derating factors for the output clock
toggle rate for a non 0 pF load.
4–98
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007