EP2SGX30C Datasheet, PDF (240/314 Pages) Altera Corporation – Stratix II GX Device

Timing Model
Table 4–57. IOE Internal Timing Microparameters (Part 2 of 2)
Symbol
Parameter
t_{PIN2COMBOUT_R} Row input pin to IOE
combinational output
t_{PIN2COMBOUT_C} Column input pin to
IOE combinational
output
t_{COMBIN2PIN_R}
Row IOE data input to
combinational output
pin
t_{COMBIN2PIN_C}
Column IOE data input
to combinational output
pin
t_CLR
Minimum clear pulse
width
t_PRE
Minimum preset pulse
width
t_CLKL
Minimum clock low
time
t_CLKH
Minimum clock high
time
-3 Speed
Grade (1)
Min Max
410 760
428 787
1101 2026
991 1854
200
200
600
600
-3 Speed
Grade (2)
Min Max
410 798
-4 Speed
Grade
Min Max
410 848
428 825 428 878
1101 2127 1101 2261
991 1946 991 2069
210
223
210
223
630
669
630
669
-5 Speed
Grade _Unit
Min Max
410 1018 ps
428 1054 ps
1101 2439 ps
991 2246 ps
268
ps
268
ps
804
ps
804
ps
Notes to Table 4–57:
(1) This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
(2) This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–58. DSP Block Internal Timing Microparameters (Part 1 of 2)
Symbol
t_SU
t_H
t_CO
Parameter
Input, pipeline, and
output register setup
time before clock
Input, pipeline, and
output register hold
time after clock
Input, pipeline, and
output register
clock-to-output
delay
-3 Speed
Grade (1)
Min Max
50
180
0
0
-3 Speed
Grade (2)
Min Max
52
189
0
0
-4 Speed
Grade
Min Max
55
200
0
0
-5 Speed
Grade _Unit
Min Max
67
ps
241
ps
0
0 ps
4–70
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007