EP2SGX30C Datasheet, PDF (302/314 Pages) Altera Corporation – Stratix II GX Device

External Memory Interface Specifications
Table 4–111. Fast PLL Specifications (Part 2 of 2)
Name
f_{OUT_EXT}
f_OUTDUTY
t_CONFIGPLL
f_CLBW
t_LOCK
t_{PLL_PSERR}
t_ARESET
t_{ARESET_RECONFIG}
Description
Min
PLL clock output frequency to regular I/O 4.6875
Duty cycle for external clock output
45
Time required to reconfigure scan chains for
fast PLLs
PLL closed-loop bandwidth
1.16
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
10
Minimum pulse width on the areset signal 500
when using PLL reconfiguration. Reset the
PLL after scandone goes high.
Typ
50
75/f_SCANCLK
5
0.03
Notes to Table 4–111:
(1) This is limited by the I/O f_MAX. See Tables 4–91 through 4–95 for the maximum.
Max
(1)
55
28
1
±30
Unit
MHz
%
ns
MHz
ms
ps
ns
ns
External
Memory
Interface
Specifications
Tables 4–112 through 4–116 contain Stratix II GX device specifications for
the dedicated circuitry used for interfacing with external memory
devices.
Table 4–112. DLL Frequency Range Specifications
Frequency Mode
Frequency Range (MHz)
0
100 to 175
1
150 to 230
200 to 350 (–3 speed grade)
2
200 to 310 (–4 and –5 speed grade)
240 to 400 (–3 speed grade)
3
240 to 350 (–4 and –5 speed grade)
Resolution
(Degrees)
30
22.5
30
30
36
36
4–132
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007