EP2SGX30C Datasheet, PDF (82/314 Pages) Altera Corporation – Stratix II GX Device

TriMatrix Memory
Figure 2–51. M4K RAM Block Control Signals
Dedicated
6
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clock_b
clocken_b
renwe_b
aclr_b
clock_a
clocken_a
renwe_a
aclr_a
The R4, C4, and direct link interconnects from adjacent LABs drive the
M4K RAM block local interconnect. The M4K RAM blocks can
communicate with LABs on either the left or right side through these row
resources or with LAB columns on either the right or left with the column
resources. Up to 16 direct link input connections to the M4K RAM block
are possible from the left adjacent LABs and another 16 possible from the
right adjacent LAB. M4K RAM block outputs can also connect to left and
right LABs through direct link interconnect. Figure 2–52 shows the M4K
RAM block to logic array interface.
2–74
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007