EP2SGX30C Datasheet, PDF (10/314 Pages) Altera Corporation – Stratix II GX Device

Transceivers
There are up to 20 transceiver channels available on a single Stratix II GX
device. Table 2–1 shows the number of transceiver channels and their
serial bandwidth for each Stratix II GX device.
Table 2–1. Stratix II GX Transceiver Channels
Device
EP2SGX30C
EP2SGX60C
EP2SGX30D
EP2SGX60D
EP2SGX60E
EP2SGX90E
EP2SGX90F
EP2SGX130G
Number of Transceiver
Channels
4
4
8
8
12
12
16
20
Serial Bandwidth
(Full Duplex)
51 Gbps
51 Gbps
102 Gbps
102 Gbps
153 Gbps
153 Gbps
204 Gbps
255 Gbps
Figure 2–2 shows the elements of the transceiver block, including the four
transceiver channels, supporting logic, and I/O buffers. Each transceiver
channel consists of a receiver and transmitter. The supporting logic
contains two transmitter PLLs to generate the high-speed clock(s) used by
the four transmitters within that block. Each of the four transmitter
channels has its own individual clock divider. The four receiver PLLs
within each transceiver block generate four recovered clocks. The
transceiver channels can be configured in one of the following functional
modes:
■ PCI Express (PIPE)
■ OIF CEI PHY Interface
■ SONET/SDH
■ Gigabit Ethernet (GIGE)
■ XAUI
■ Basic (600 Mbps to 3.125 Gbps single-width mode and 1 Gbps to
6.375 Gbps double-width mode)
■ SDI (HD, 3G)
■ CPRI (614 Mbps, 1228 Mbps, 2456 Mbps)
■ Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)
2–2
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007