EP2SGX30C Datasheet, PDF (283/314 Pages) Altera Corporation – Stratix II GX Device

DC and Switching Characteristics
Table 4–96. Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Series Termination) (Part
2 of 2)
I/O Standard Drive Strength -3 Speed Grade -4 Speed Grade -5 Speed Grade
SSTL-18 Class II OCT_25_OHMS
550
500
450
1.5-V HSTL
OCT_50_OHMS
600
550
500
Class I
1.8-V HSTL
OCT_50_OHMS
650
600
600
Class I
1.8-V HSTL
OCT_25_OHMS
500
500
450
Class II
DIfferential
OCT_50_OHMS
600
500
500
SSTL-2 Class I
DIfferential
OCT_25_OHMS
600
550
500
SSTL-2 Class II
DIfferential
OCT_50_OHMS
560
400
350
SSTL-18 Class I
DIfferential
OCT_25_OHMS
550
500
450
SSTL-18 Class II
1.8-V differential OCT_50_OHMS
650
600
600
HSTL Class I
1.8-V differential OCT_25_OHMS
500
500
450
HSTL Class II
1.5-V differential OCT_50_OHMS
600
550
500
HSTL Class I
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4–97 specifies the derating factors for the output clock toggle rate
for a non 0 pF load.
Table 4–97. Maximum Output Clock Toggle Rate Derating Factors (Part 1 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
Drive
Strength
Column I/O Pins
Row I/O Pins
Dedicated Clock
Outputs
3.3-V LVTTL
-3
-4
-5
-3
-4 -5 -3 -4 -5
4 mA
478 510 510 478 510 510 466 510 510
8 mA
260 333 333 260 333 333 291 333 333
12 mA 213 247 247 213 247 247 211 247 247
16 mA 136 197 197
-
-
-
166 197 197
20 mA 138 187 187
-
-
-
154 187 187
24 mA 134 177 177
-
-
-
143 177 177
Altera Corporation
October 2007
4–113
Stratix II GX Device Handbook, Volume 1