EP2SGX30C Datasheet, PDF (218/314 Pages) Altera Corporation – Stratix II GX Device

Operating Conditions
Table 4–31. 3.3-V PCML Specifications
Symbol
V_CCIO
V_ID
V_ICM
V_OD
ΔV_OD
V_{O C M}
ΔV_{O C M}
V_T
R₁
R₂
Parameter
I/O supply voltage
Input differential voltage
swing (single-ended)
Input common mode
voltage
Output differential voltage
(single-ended)
Change in V_{O D} between
high and low
Output common mode
voltage
Change in V_{O C M} between
high and low
Output termination voltage
Output external pull-up
resistors
Output external pull-up
resistors
Conditions
Minimum
3.135
300
Typical
3.3
Maximum
3.465
600
Units
V
mV
1.5
3.465
V
300
370
500
mV
50
mV
2.5
2.85
3.3
V
50
mV
V_{C C I O}
V
45
50
55
Ω
45
50
55
Ω
Table 4–32. LVPECL Specifications
Symbol
Parameter
Conditions
V_CCIO (1)
V_ID
I/O supply voltage
Input differential voltage
swing (single-ended)
V_ICM
V_OD
V_OCM
Input common mode voltage
Output differential voltage
(single-ended)
R_L = 100 Ω
Output common mode
voltage
R_L = 100 Ω
R_L
Receiver differential input
resistor
Minimum
3.135
300
1.0
525
1,650
90
Typical
3.3
600
100
Maximum Unit
3.465
V
1,000 mV
2.5
V
970
mV
2,250 mV
110
Ω
Note to Table 4–32:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V_CCINT, not V_CCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
4–48
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007