EP2SGX30C Datasheet, PDF (15/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer resides in the
transceiver block at the PCS/FPGA boundary and cannot be bypassed.
This FIFO buffer compensates for phase differences between the
transmitter PLL clock and the clock from the PLD. After the transmitter
PLL has locked to the frequency and phase of the reference clock, the
transmitter FIFO buffer must be reset to initialize the read and write
pointers. After FIFO pointer initialization, the PLL must remain phase
locked to the reference clock.
Byte Serializer
The FPGA and transceiver block must maintain the same throughput. If
the FPGA interface cannot meet the timing margin to support the
throughput of the transceiver, the byte serializer is used on the
transmitter and the byte deserializer is used on the receiver.
The byte serializer takes words from the FPGA interface and converts
them into smaller words for use in the transceiver. The transmit data path
after the byte serializer is 8, 10, 16, or 20 bits. Refer to Table 2–3 for the
transmitter data with the byte serializer enabled. The byte serializer can
be bypassed when the data width is 8, 10, 16, or 20 bits at the FPGA
interface.
Table 2–3. Transmitter Data with the Byte Serializer Enabled
Input Data Width
16 bits
20 bits
32 bits
40 bits
Output Data Width
8 bits
10 bits
16 bits
20 bits
If the byte serializer is disabled, the FPGA transmit data is passed without
data width conversion.
Altera Corporation
October 2007
2–7
Stratix II GX Device Handbook, Volume 1