EP2SGX30C Datasheet, PDF (130/314 Pages) Altera Corporation – Stratix II GX Device

I/O Structure
Figure 2–85. Output Timing Diagram in DDR Mode
CLK
From Internal
Registers
A1
A2
A3
A4
B1
B2
B3
B4
DDR output
B1 A1 B2 A2 B3 A3 B4 A4
The Stratix II GX IOE operates in bidirectional DDR mode by combining
the DDR input and DDR output configurations. The
negative-edge-clocked OE register holds the OE signal inactive until the
falling edge of the clock to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Stratix II GX devices also
have dedicated phase-shift circuitry for interfacing with external memory
interfaces, including DDR and DDR2 SDRAM, QDR II SRAM,
RLDRAM II, and SDR SDRAM. In every Stratix II GX device, the I/O
banks at the top (banks 3 and 4) and bottom (banks 7 and 8) of the device
support DQ and DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18,
or ×32/×36. Table 2–31 shows the number of DQ and DQS buses that are
supported per device.
Table 2–31. DQS and DQ Bus Mode Support
Device
Package
EP2SGX30 780-pin FineLine BGA
EP2SGX60 780-pin FineLine BGA
1,152-pin FineLine BGA
EP2SGX90 1,152-pin FineLine BGA
1,508-pin FineLine BGA
EP2SGX130 1,508-pin FineLine BGA
Number of Number of
×4 Groups ×8/×9 Groups
18
8
18
8
36
18
36
18
36
18
36
18
Number of
×16/×18
Groups
4
4
8
8
8
8
Number of
×32/×36
Groups
0
0
4
4
4
4
2–122
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007