EP2SGX30C Datasheet, PDF (121/314 Pages) Altera Corporation – Stratix II GX Device

Stratix II GX Architecture
Figure 2–77 shows how a row I/O block connects to the logic array.
Figure 2–77. Row I/O Block Connection to the Interconnect
R4 & R24
Interconnects
C4 Interconnect
I/O Block Local
Interconnect
32 Data & Control
Signals from
Logic Array (1)
LAB
32
Horizontal
I/O Block
io_dataina[3..0]
io_datainb[3..0]
Direct Link
Interconnect
to Adjacent LAB
LAB Local
Interconnect
Direct Link
Interconnect
to Adjacent LAB
io_clk[7:0]
Horizontal I/O
Block Contains
up to Four IOEs
Note to Figure 2–77:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
Altera Corporation
October 2007
2–113
Stratix II GX Device Handbook, Volume 1