EP2SGX30C Datasheet, PDF (293/314 Pages) Altera Corporation – Stratix II GX Device

DC and Switching Characteristics
Therefore, the DCD percentage for the output clock is from 48.4% to
51.6%.
Table 4–101. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 and -5
Devices Note (1)
Maximum DCD (ps) for
Input I/O Standard (No PLL in the Clock Path)
Row DDIO Output I/O
TTL/CMOS
SSTL-2 SSTL/HSTL
LVDS
Unit
Standard
3.3/2.5V 1.8/1.5V
2.5V
1.8/1.5V
3.3V
3.3-V LVTTL
440
495
170
160
105
ps
3.3-V LVCMOS
390
450
120
110
75
ps
2.5 V
375
430
105
95
90
ps
1.8 V
325
385
90
100
135
ps
1.5-V LVCMOS
430
490
160
155
100
ps
SSTL-2 Class I
355
410
85
75
85
ps
SSTL-2 Class II
350
405
80
70
90
ps
SSTL-18 Class I
335
390
65
65
105
ps
1.8-V HSTL Class I
330
385
60
70
110
ps
1.5-V HSTL Class I
330
390
60
70
105
ps
LVDS
180
180
180
180
180
ps
Note to Table 4–101:
(1) Table 4–101 assumes the input clock has zero DCD.
Table 4–102. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2) Note (1)
Maximum DCD (ps) for
Input IO Standard (No PLL in the Clock Path)
DDIO Column Output I/O
TTL/CMOS
SSTL-2 SSTL/HSTL HSTL12
Unit
Standard
3.3/2.5V 1.8/1.5V
2.5V
1.8/1.5V
1.2V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
260
380
145
145
145
ps
210
330
100
100
100
ps
195
315
85
85
85
ps
150
265
85
85
85
ps
255
370
140
140
140
ps
175
295
65
65
65
ps
170
290
60
60
60
ps
155
275
55
50
50
ps
Altera Corporation
October 2007
4–123
Stratix II GX Device Handbook, Volume 1